Principal Analog/Mixed-Signal ASIC Design Engineer

4 дн. назад

СШАLeadHybrid

asic designanalog circuit designmixed-signal designverificationlayout

Principal engineer role responsible for Analog/Mixed-Signal ASIC design, verification, layout and tape-out for wireless optical communication R&D.

Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of people who lack abundant and affordable internet by pioneering high-throughput, long-range free-space optical communication (FSOC). Our links use eye-safe lasers propagating between two terminals to transmit high-speed data wirelessly. Lead the charge in bringing our groundbreaking wireless optical communication to the world. Join us to light the way toward bridging the digital divide and illuminating the future.

Taara is seeking a Principal Analog/Mixed-Signal ASIC Design Engineer to work on the next generation of co-integrated electronic and photonic modules. You will be part of an R&D team developing cutting-edge wireless optical communication systems based on integrated optical phased arrays.
The successful candidate will own ASIC design blocks and contribute to the tape-out, delivery, and validation of ASIC dies, working with a small team of ASIC design, layout, and test engineers. The role involves hands-on contributions to Analog/Mixed-Signal (AMS) ASIC design, verification, and layout. It also requires extensive ASIC design experience—including multiple ASIC tape-outs at leading commercial foundries—and deep expertise in high-precision AMS circuits such as analog-to-digital and digital-to-analog converters.
We are looking for a highly motivated individual who thrives in ambiguity, enjoys working in a small, dynamic team environment, and has a passion for solving challenging problems that lead to high-impact technological advances.

Expertise in planning and executing the verification of large Systems-on-Chip (SoCs) that incorporate complex digital logic and numerous custom-designed blocks.
Fluency in hardware description languages, such as Register-Transfer Level (RTL) code, and RTL-to-GDS design flows using industry-standard EDA tools.
Experience with versioning tools such as SOS and Git.
Proficiency with commercial layout verification software (Calibre or equivalent).
Excellent communication and presentation skills, with the ability to work effectively with senior external partners.
A track record of advancing a product from the prototype phase to the final production stage.

A hybrid or onsite setup in Sunnyvale, CA, is preferred, though remote work can be considered. Relocation assistance can be provided.
The US salary range for this full-time position is $258,000 - $294,000 (inclusive of bonus at target) + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your location during the hiring process.

Own and deliver custom ASIC blocks for co-integration with large-scale photonic integrated circuits to form record-breaking integrated modules.
Contribute to chip architecture, system-level optimization, and product strategy.
Demonstrate a strong motivation to improve the world through technology and a desire to be part of the team making it happen.
Ph.D. in Electrical Engineering or a related field.
10 or more years of relevant industry experience with demonstrated achievements in analog/mixed-signal circuit design and implementation in modern CMOS technologies.
Deep design expertise in high-precision circuits such as analog-to-digital and digital-to-analog converters, bandgap references, voltage regulators, amplifiers, and other supporting circuitry.
Tapeout experience in high voltage Bipolar-CMOS-DMOS (BCD) technology including successful silicon bring-up and characterization.
Extensive background in the integration and co-simulation of analog and digital circuits in the context of mixed-signal design and verification.
Hands-on experience contributing to multiple ASIC tape-outs at commercial foundries including chip top-level ownership.
Hands-on experience with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Power Integrity (PI), and Signal Integrity (SI) verification."