СШАStaff SoC RTL Engineer
4 нед. назад
СШАLeadOnsite
rtlsystemverilogip integrationsoc architecturepci-expressddrsecurity
Staff engineer role responsible for SoC architecture definition, subsystem development, 3rd party IP integration, and optimization at , an edge AI hardware company.
Обязанности
- is building a revolutionary new processor-based SoC architecture. As a Staff SoC RTL Engineer , you will get in on the ground floor as a key member of our chip design team, contributing across all stages of the SoC design and integration cycle. In this role, you will help define the SoC architecture, own subsystem development, integrate third-party IP, and drive PPA optimization to bring our next-generation platform to life.
- Within your first 6–12 months, you'll:
- Independently own SoC subsystem development and drive measurable PPA improvements.
- Develop an in-depth understanding of the architecture and software interfaces, enabling you to debug complex issues across the full SW/HW stack.
- Successfully package and deliver design releases for customer evaluation and integration.
Будет плюсом
- Experience in logic synthesis and performance modeling.
- Experience in FPGA design.
- Familiarity with automotive safety standards (ASIL) and hardware security standards.
Условия
- The base salary range for this position is $170,000 to $230,000. This range reflects the full span of levels and geographies at which hires for this role. The actual base salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies, the criticality of the role to the business, internal equity, and work location. In addition to base salary, this role is eligible for equity and a discretionary annual performance bonus as applicable to the role and level.
- In addition to a competitive salary, we offer a variety of benefits to support your needs. The benefits below reflect our US-based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:
- Medical, dental, and vision insurance from day one - Premiums covered at 99% for Employees
- Company-paid life Insurance
- Voluntary supplemental life insurance
- STD + LTD insurance
- Commuter support including parking or Caltrain reimbursement. Our office is conveniently located within walking distance of the Caltrain station
- FSA + HSA
- Equity with the business
- Paid Parental Leave
- 401(k) Retirement Plan
- Flexible PTO
- Winter holiday shutdown
- Catered lunch each day in our office
- Downtown Burlingame office location, close to shops, cafes, and local amenities
- Collaborative, low-ego culture with significant ownership and impact
- A work culture focused on innovative disruption
- If this role resonates with you, we encourage you to apply even if your experience does not perfectly match every qualification. We value potential, curiosity, and a willingness to learn just as much as direct experience.
Другое
- is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.
- Founded in 2016 and based in downtown Burlingame, California, is building the world's first supercomputer designed for the real-time needs of edge devices. aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.
- Own SoC-level subsystem development and seamless integration with third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
- Contribute directly to the definition of the SoC architecture by deeply understanding its application requirements.
- Package designs for customer releases and rapidly iterate based on customer feedback.
- Own Power, Performance, and Area (PPA) optimization strategies at the SoC level.
- Apply low-power digital design techniques to optimize hardware efficiency.
- Contribute to timing closure across the full product lifecycle, spanning front-end, back-end, and final tapeout stages.
- Balance single-stream latency against scaled throughput performance.
- BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience.
- Proficiency in SystemVerilog or Verilog.
- Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem (Memory, I/O, or Compute).
- Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation.
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