СШАStaff Deep Learning Compiler Engineer
4 нед. назад
СШАLeadOnsite
mlirtvmllvmc++compilerdeep learning
Design and optimize the compiler stack for neural network frameworks targeting proprietary hardware architecture to enhance edge AI performance.
Обязанности
- is building the world’s first General-Purpose Neural Processing Unit (GPNPU) architecture, bringing high-performance AI, DSP, and ML compute to edge devices. As a Deep Learning Compiler Engineer , you will design and optimize the compiler stack (MLIR, TVM, LLVM) that bridges state-of-the-art neural network frameworks directly to our proprietary hardware architecture. You'll play a critical role in unlocking peak hardware performance, low latency, and memory efficiency for edge AI workloads.
Будет плюсом
- Experience with low-level kernel optimization, SIMD/vector programming, and memory allocation strategy development.
- Knowledge of model quantization methodologies (INT8, FP8, mixed-precision) and post-training/QAT optimization techniques.
- Prior experience working on software stacks for custom AI accelerators, DSPs, or embedded architectures.
- Experience with FPGA bring-up, hardware emulation, or cycle-accurate simulator development.
- also offer a variety of benefits to support your needs. The benefits below reflect our US-based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:
- Medical, dental, and vision insurance from day one - Premiums covered at 99% for Employees
- Company-paid life Insurance
- Voluntary supplemental life insurance
- STD + LTD insurance
- Commuter support including parking or Caltrain reimbursement. Our office is conveniently located within walking distance of the Caltrain station
- FSA + HSA
- Equity with the business
- Paid Parental Leave
- 401(k) Retirement Plan
- Flexible PTO
- Winter holiday shutdown
- Catered lunch each day in our office
- Downtown Burlingame office location, close to shops, cafes, and local amenities
- Collaborative, low-ego culture with significant ownership and impact
- A work culture focused on innovative disruption
- If this role resonates with you, we encourage you to apply even if your experience does not perfectly match every qualification. We value potential, curiosity, and a willingness to learn just as much as direct experience.
Условия
- The base salary range for this position is $170,000 to $230,000. This range reflects the full span of levels and geographies at which hires for this role. The actual base salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies, the criticality of the role to the business, internal equity, and work location. In addition to base salary, this role is eligible for equity and a discretionary annual performance bonus as applicable to the role and level.
Другое
- is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.
- Founded in 2016 and based in downtown Burlingame, California, is building the world's first supercomputer designed for the real-time needs of edge devices. aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.
- Design, implement, and maintain compiler optimization passes targeting ’s processor architecture using frameworks like MLIR, Apache TVM, or LLVM.
- Develop lowering pathways from high-level machine learning frameworks (PyTorch, TensorFlow, ONNX) down to optimized low-level kernel code.
- Optimize neural network performance for memory throughput, latency, compute unit utilization, and power consumption.
- Implement graph-level optimizations, including operator fusion, layout transformation, quantization (INT8/FP16), and memory allocation strategies.
- Analyze novel deep learning model topologies (Transformers, CNNs, Vision-Language Models) and extend compiler support for new operators and primitives.
- Benchmark and profile end-to-end model performance to identify and resolve compiler bottlenecks.
- Collaborate closely with hardware and micro-architecture teams to define instruction set extensions, hardware acceleration features, and compiler requirements.
- Develop software simulators, functional models, and test benches to validate compiler correctness and generated binary performance.
- Participate in hardware bring-up and validation efforts on FPGA and ASIC platforms.
- Successfully integrate support for key deep learning models (e.g., modern Transformer architectures or Vision models) into 's compiler pipeline.
- Implement custom graph and codegen optimization passes that deliver measurable performance improvements on target benchmarks.
- Partner with the architecture team to influence the next-generation micro-architecture definition through data-driven workload analysis.
- BS, MS, or Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
- 8+ years Hands-on experience developing deep learning compilers or compiler infrastructures (e.g., MLIR, Apache TVM, LLVM, XLA, TensorRT, or Glow).
- Strong proficiency in C++ (14/17/20) and Python, with solid fundamentals in data structures, algorithms, and object-oriented design.
- Familiarity with modern AI/ML frameworks (PyTorch, TensorFlow, ONNX) and deep learning operator representations.
- Solid understanding of computer systems, memory hierarchies, parallel processing, and CPU/GPU/NPU instruction execution.
- By submitting an application, you acknowledge that will collect and process your personal information as part of the hiring process. Please review our Privacy Policy to understand how we handle your data