СингапурIC Layout Engineer – Optical Engine Silicon
3 нед. назад
Сингапур
layoutmixed-signalanalogphotonicparasitic extractiondrclvs
Responsible for electronic and photonic IC layout focusing on high-speed analog and mixed-signal blocks for optical engine silicon in AI data centers.
Обязанности
- builds optical interconnect for AI data centers: silicon photonics, mixed-signal ICs, electrical-optical interposers, and the systems around them. Our silicon ships in production AI clusters today, and volume is climbing fast.
- You will own layout for our electronic ICs (EICs) and photonic ICs (PICs). These are high-speed analog blocks where the layout is the design: a parasitic you did not anticipate, a return path you did not control, or a current density you did not check will cost the part its margin.
- You will also support photonic IC (PIC) layout as our schedule demands, and own the integration of electronic and photonic dies as they come together.
- Singapore puts you close to the assembly and test supply chain we depend on, working alongside a senior layout engineer and partnering with design teams across the US, India, and Singapore.
- Own layout for assigned analog and mixed-signal blocks: device placement, matching and symmetry, shielding, guard rings, and routing, from floorplan through to clean sign-off.
- Execute parasitic-aware layout — build to the constraints given by designers, run extraction, and take the results back to them when the layout says something the schematic did not expect.
- Route high-speed signal paths with attention to impedance, coupling, and return paths, and lay out passive and electromagnetic structures under senior direction.
- Run and close DRC, LVS, antenna, and density checks on your blocks, and support electromigration and IR drop analysis.
- Support top-level assembly and chip finishing activities through tape out.
- Support PIC layout as the need arises, including waveguide and curvilinear structures.
- Lay out photonic components and waveguide routing — bends, tapers, couplers, grating and edge couplers, and modulator and photodetector electrodes — from designer-provided geometry, honoring minimum bend radius, waveguide spacing, and phase- and length-matching constraints.
- Run photonics-specific verification: curvilinear DRC against the photonics PDK, waveguide connectivity and port checks, LVS on custom photonic cells, and clean GDS stream-out for tape out.
- Build the scripts and reusable structures that make the layout team faster.
Требования
- Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
- 1–3 years in custom analog, RF, or mixed-signal IC layout, including at least one tapeout you contributed to through to silicon.
- Solid working experience with Cadence Virtuoso, including Layout XL and constraint-driven flows.
- Parasitic awareness in practice — you understand why a matched pair is drawn the way it is, and which nets on your block deserve the extra care.
- Fundamentals in electromigration and IR drop: current density limits, power routing, and the checks that catch problems.
- Fundamentals in electromagnetics for on-chip structures — coupling, shielding, and why high-speed routing is constrained the way it is.
- Physical verification experience: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
- Some scripting for layout automation — SKILL, Python, or both.
- Willingness to overlap with US and India hours during tape out crunch.
Будет плюсом
- SiGe BiCMOS layout experience, and the passive and isolation practices those processes demand.
- Advanced FinFET CMOS layout at 7nm and below — multi-patterning and coloring, fin and poly grid constraints, and the DRC complexity that comes with them.
- Photonic IC layout exposure: waveguide routing, curvilinear geometry, and photonics PDK design rules.
- Experience with parametric photonic cells (PCells) in Virtuoso SKILL or Python-based photonic layout tools (gdsfactory, KLayout, IPKISS), and with curvilinear-to-grid snapping and fracture rules.
- Familiarity with silicon photonics building blocks and their layout sensitivities: Mach-Zehnder and ring modulators, Ge photodetectors, thermal phase shifters, and fiber coupling structures.
- Exposure to 2.5D and 3D integration, interposers, or micro-bump and copper pillar arrays.
- Layout on optical front ends specifically — TIA, modulator driver, or high-speed serial link blocks.
Другое
- Optical I/O for AI is being defined right now, and in this silicon the layout is where the performance is actually won. The team is small, so the blocks are yours: you will take them from floorplan to tapeout, see them come back as working parts, and grow into top-level and methodology ownership as we scale. You will also get a working foot in photonics, which very few layout engineers have.