Principal Physical Design Engineer

3 нед. назад

USALead

physical designfloorplanningtiming analysispower optimizationsignoffrtltapeout

Lead physical design and backend implementation of high-performance SoCs for AI infrastructure, driving critical decisions and mentoring engineers.

End-to-End RTL2GDS Ownership 
Own the full RTL2GDS flow on advanced process nodes — synthesis, floorplan, placement, CTS, routing, and signoff — across Astera's connectivity product portfolio 
Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs 
Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets 
Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab 
Timing, Power & Signoff 
Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff 
Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure 
Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around 
Technical Leadership & Cross-Functional Partnership 
Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to converge on floorplan, clocking, and power delivery strategies 
Establish and evolve physical design methodology, scripts, and flows across the team 
Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field 
8+ years of physical design experience with multiple tapeouts on advanced process nodes (7nm or below) 
Deep expertise in synthesis, place & route, CTS, and timing closure using industry-standard tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, PrimeTime) 
Strong command of low-power design techniques (multi-Vt, power gating, DVFS, UPF) 
Proficiency in Tcl/Python scripting for flow automation 
Proven track record delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production

MS in Electrical Engineering or Computer Engineering 
Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs 
Hands-on experience with hierarchical implementation and full-chip integration of large designs (>500M gates) 
Familiarity with EMIR, thermal, and package co-design considerations 
Experience mentoring senior engineers and driving methodology adoption across teams 
Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. 
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at.
Astera Labs is redefining the connectivity fabric that powers rack-scale AI infrastructure. As a Principal Engineer on the Physical Design team, you will own the backend implementation of complex, high-performance SoCs that sit at the heart of the world's largest AI clusters — driving floorplan, timing, power, and signoff decisions that directly determine product PPA and time-to-market. 
This is a hands-on technical leadership role. You will architect physical design methodology, mentor senior engineers, and partner closely with RTL, DFT, analog, and package teams to take our next generation of connectivity silicon from RTL to tapeout on leading-edge nodes.