Principal SerDes Bring-up Validation Engineer (2026-376)

4 нед. назад

USALeadOnsite

serdesvalidationpost-siliconcharacterizationlab work

Lead post-silicon bring-up, validation, and characterization of SerDes technology for AI infrastructure connectivity solutions.

Будет плюсом

MS or PhD in Electrical Engineering or a related field to demonstrate advanced technical depth and specialization.
Hands-on proficiency with signal integrity test equipment and methodologies (BERTs, VNAs, oscilloscopes, sampling scopes, TDRs, advanced probing) and experience designing and debugging lab characterization and demo boards.
Working knowledge of IEEE 802.3 Ethernet standards and experience validating Ethernet PHYs, link training, auto-negotiation, and compliance across speeds and media types.
Practical understanding of serial interfaces such as I2C, I3C, SPI, and UART for device bring-up, firmware interaction, and system integration.
Proven ability to translate SI/PI simulation results into testable lab plans and document findings that drive design or process improvements.
Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Другое

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at.
 
Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer to join a cutting-edge mixed-signal design team and lead end-to-end post-silicon bring-up, validation, and characterization. You will own bring-up and characterization strategies from the ground up, translating design and product requirements into measurable test objectives, pass/fail criteria, and schedules, and driving hands-on lab work to verify silicon against specification and performance targets.
As a hyper-growth company building the purpose-built connectivity that powers rack-scale AI infrastructure, the speed and rigor of our silicon validation directly shape what we can ship. You will partner closely with AMS design, firmware, and system teams to build automated test frameworks, debug complex analog and digital interactions at the physical layer, and deliver clear, data-driven recommendations that influence product direction. This is a high-impact role for a deep technical expert who thrives on hands-on problem solving and mentoring across disciplines.
Key Responsibilities  
Design, develop, and execute bring-up plans. Own end ‑ to ‑ end post ‑ silicon bring up and characterization strategies, translating design/product requirements into measurable test objectives, pass/fail criteria, and schedules.  
Drive design reviews and specification alignment. Participate in architecture and design ‑ spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.  
Lead hands ‑ on test execution and bring ‑ up. Perform silicon block level bring ‑ up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time ‑ to ‑ data.  
Build and maintain automation frameworks. Develop scalable test automation, data capture, and analysis pipelines to increase throughput, reproducibility, and coverage across mixed ‑ signal test benches.  
Debug and optimize system performance. Diagnose complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers; propose and validate corrective actions to improve stability, yield, and power/performance tradeoffs.  
Root ‑ cause cross ‑ domain failures. Trace issues to circuit, package, firmware, or protocol interactions using lab measurements, waveform analysis, and system ‑ level tests; coordinate with design, package, and firmware teams to implement fixes.  
Collaborate with cross ‑ functional teams. Work closely with mixed ‑ signal design, firmware, system engineering, and manufacturing to deliver detailed results, root ‑ cause analyses, optimization recommendations, and formal validation/compliance reports.  
Document findings and improve methodologies. Produce clear debug reports, formal characterization summaries, and recommendations for design/process/test improvements; contribute to failure analysis (FA) best practices and knowledge base.  
Develop test software and platform integrations. Write robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms, improving firmware stability and automating regression suites.  
Measure and communicate impact. Define key validation metrics, track coverage and defect trends, and present data ‑ driven conclusions to stakeholders to influence product direction and release decisions.   Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
8-12 years of hands-on experience in mixed-signal, high-speed lab environments executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.
Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers, with a strong understanding of the physical layer and experience developing characterization flows and validating silicon against specifications.
Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization), with the ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.
Practical experience bringing up and debugging retimers, including equalization tuning, pass-through operation, clocking strategies, and reset and link sequencing.
Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction, paired with exceptional troubleshooting skills and excellent written and verbal communication.