Furiosa Ai
Senior Design Verification Engineer
7mo ago
WorldwideSeniorsystemveriloguvmeda-toolspythonperlshellcocotb
Lead design verification processes using SystemVerilog/UVM and EDA tools to ensure high design quality in collaboration with cross-functional teams.
Responsibilities
- Define, plan, and implement block and system level verification strategies
- Write and review test plans, develop test harnesses and test sequences
- Drive the design verification process to successful closure by meeting defined verification metrics across the test plan, functional coverage, and code coverage
- Collaborate closely with the Design team to debug, root-cause, and resolve functional failures within the design
- Work collaboratively with cross-functional teams, including Design, Model, Emulation, and Silicon Validation, to ensure the highest standards of design quality
Requirements
- Bachelor's degree in Electrical Engineering, Computer Science, or a closely related technical field
- 5+ years of experience in block and system level verification utilizing SystemVerilog/UVM-based methodologies
- Proven experience with Electronic Design Automation (EDA) tools and proficiency in scripting languages (Python, Perl, Shell) for developing verification tools and flows
- Experience in architecting and deploying Design Verification infrastructure, including executing the complete verification cycle from planning to closure
Nice to have
- Master’s degree in Electrical Engineering, Computer Science, or a closely related technical field
- Expertise in developing UVM-based verification environments from initial setup
- Expertise in developing Python-based verification environment such as cocotb
- Experience in IP or integration verification for high-speed interfaces such as PCIe, UCIe, UALink, and Ethernet
- Experience verifying ARM/RISC-V-based sub-systems or SoCs
- Strong Python programming skills
- Excellent written and verbal communication skills